1/9 ESDA14V2-4BF1 quad bidirectional transil? array for esd protection ? description the ESDA14V2-4BF1 is a monolithic array designed to protect up to 4 lines in a bidirectional way against esd transients. the device is ideal for situations where board space saving is requested. july 2002 - ed: 6b where transient overvoltage protection in esd sensitive equipment is required, such as : n computers n printers n communication systems and cellular phones n video equipment this device is particularly adapted to the protection of symmetrical signals. applications flip chip package gnd a1 a3 c1 c3 functional diagram a.s.d? n high esd protection level n high integration n suitable for high density boards benefits - iec61000-4-2: 15 kv (air discharge) 8 kv (contact discharge) - mil std 883e-method 3015-7: class3 25kv (human body model) complies with the following standards: n 4 bidirectional transil? functions n esd protection: iec61000-4-2 level 4 n stand off voltage: 12 v min. n low leakage current < 1 m a n 50w peak pulse power ( 8/20 ) features a b c 31 2 pin configuration (ball side)
ESDA14V2-4BF1 2/9 symbol test conditions value unit v pp esd discharge - mil std 883e - method 3015-7 iec61000-4-2 air discharge iec61000-4-2 contact discharge 25 15 8 kv p pp peak pulse power (8/20 m s) 50 w t j junction temperature 125 c t stg storage temperature range -55 to +150 c t l lead solder temperature (10 seconds duration) 260 c t op operating temperature range (note 1) -40 to +125 c note 1: variation of parameters will be given in the final datasheet absolute ratings (t amb = 25c) symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current i pp peak pulse current c capacitance rd dynamic resistance electrical characteristics (t amb = 25c) i v v br cl v rm i pp i rm v slope = 1/rd type v br @i r i rm @v rm rd tc min. max. max. typ. max. max note 1 note 2 0v bias vvma m av w 10 -4 /c pf esda14v2- 4bf1 14.2 18 1 112 3.2 10 15 0.1 3 note 1: square pulse, i pp = 3a, tp = 2.5 m s note 2 : d vbr = a t(tamb-25c) x vbr(25c)
ESDA14V2-4BF1 3/9 0.1 1.0 10.0 0 102030405060 vcl(v) ipp(a) tp = 2.5s fig. 1: clamping voltage versus peak pulse current (tj initial = 25c) rectangular waveform tp = 2.5s. 0 2 4 6 8 10 12 14 02468101214 vr(v) f=1mhz vosc=30mv rms tj=25c c(pf) fig. 2: capacitance versus reverse applied voltage (typical values). 1 10 100 1000 25 50 75 100 125 tj(c) ir[tj] / ir[tj=25c] fig. 3: relative variation of leakage current versus junction temperature (typical values). connector ic to be protected a1 a3 c1 c3 b2 application example
ESDA14V2-4BF1 4/9 with the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. electrostatic discharge (esd) is a major cause of failure in electronic systems. as a transient voltage suppressor, ESDA14V2-4BF1 is an ideal choice for esd protection by suppressing esd events. it is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDA14V2-4BF1. ESDA14V2-4BF1 serves as a parallel protection elements, connected between the signal line and ground. as the transient rises above the operating voltage of the device, the ESDA14V2-4BF1 becomes a low impedance path diverting the transient current to ground. the clamping voltage is given by the following formula: vv ri cl br d pp =+ . as shown in figure a1, the esd strikes are clamped by the transient voltage suppressor. 1. esd protection by esda14v2- 4bf1 technical information ESDA14V2-4BF1 rg rd v br vg r load esd surge device to be protected v(i/o) ip fig. a1: esd clamping behavior to have a good approximation of the remaining voltages at both vi/o side, we provide the typical dynamical resistance value rd. by taking into account the following hypothesis : r g >r d and rload > r d we have: vi o v r v r br d g g (/ ) =+ the results of the calculation done for v g = 8 kv, r g = 330 w (iec 61000-4-2 standard), v br = 14.2 v (min.) and r d = 3.2 w (typ.) give: v(i/o) = 91.8 v this confirms the very low remaining voltage across the device to be protected. it is also important to note that in this approximation the parasitic inductance effect was not taken into account. this could be a few tenths of volts during a few ns at the vi/o side.
v(i/o) 5/9 ESDA14V2-4BF1 fig. a2: esd test board test board v(i/o) eb14 15 ? fig. a4: remaining voltage during esd surge fig. a3: esd test configuration v(i/o) b2 a1, c1, a3 or c3 15kv esd air discharge the measurements done here after show very clearly (fig. a4) the high efficiency of the esd protection: the clamping voltage v(i/o) becomes very close to +v br (positive way, fig. a4a) and -v br (negative way, fig. a4b). v(i/o) v(i/o) a: response in the positive way b: response in the negative way
6/9 ESDA14V2-4BF1 line 1 line 2 v g1 v g2 r g1 r g2 drivers r l1 r l2 receivers ab 1g1 12g2 v+ v ab 2g2 21g1 v+ v fig. a5: crosstalk phenomenon crosstalk behavior the crosstalk phenomena are due to the coupling between 2 lines. coupling factors ( b 12 or b 21 ) increase when the gap across lines decreases, particularly in silicon dice. in the example above, the expected signal on load r l2 is a 2 v g2 , in fact the real voltage at this point has got an extra value b 21 v g2 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. the perturbed line will be more affected if it works with low voltage signal or high load test board eb14 15 a1 c3 connected to the port1 of the network analyser connected to the port2 of the network analyser fig. a6: analog crosstalk measurements
ESDA14V2-4BF1 7/9 100.0k 1.0m 10.0m 100.0m 1.0g -100.0 -90.00 -80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00 f/hz typical crosstalk response of ESDA14V2-4BF1 (a1/a3 line) fig. a7: typical analog crosstalk measurements figure a6 gives the measurement circuit for the analog crosstalk application. in figure a7, the curve shows the effect of the line a1 on the line a3. in usual frequency range of analog signals (up to 100mhz) the effect on disturbed line is less than -30db. a1 c3 unloaded unloaded b 21 g1 v b2 = gnd v g1 pulse generator f = 5mhz risetime = 3ns 0 - 3v fig. a8: digital crosstalk measurements configu- ration. v g1 b 21 g1 v rise time: t = 3ns 10-90% crosstalk fig. a9: digital crosstalk results figure a8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. figure a9 shows that in such a condition, the impact on the disturbed line is less than 50 mv peak to peak. no data disturbance was noted on the concerned line. the measurements performed with falling edges give an impact within the same range.
8/9 ESDA14V2-4BF1 esda 14v2 - 4 b f 1 esd array v min br flip chip nb of lines bidirectional pitch & bump defined below order code 100m 1.2pf 100m 50ph 50m 160ph 1.8 b2 1.2pf 100m 1.2pf 100m 1.2pf d02_r c3 a3 c1 b2 a1 d02_r bv = 16 ibv = 1m cjo = 200p m = 0.3333 rs = 1 vj = 0.6 tt = 100n d02_f bv = 16 ibv = 1m cjo = 10.4p m = 0.3333 rs = 2 vj = 0.6 tt = 100n fig. a10: aplac model
ESDA14V2-4BF1 9/9 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap- proval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore spain - sweden - switzerland - united kingdom - united states. http://www.st.com 1270 50 1270 50 700 50 315 50 495 50 650 65 package mechanical data die size (all dimensions in m) eat yww 265 1270 1270 200 diam 230 220 275 40 ? marking ordering code marking package weight base qty delivery mode ESDA14V2-4BF1 eat flip-chip 2.1 mg 5000 tape & reel 7 other information note: more packing informations are available in the application note an1235: "flip-chip: package de- scription and recommandations for use" n yww: date code
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